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Dual Low Drop Voltage Regulator
TLE 4473 GV55-2
Features * * * * * * * * * * * * Stand-by output 190 mA; 5 V 2% Main output: 300 mA, 5 V tracked to the stand-by output Low quiescent current consumption Disable function separately for both outputs Wide operation range: up to 42 V Very low dropout voltage 2 independent reset circuits Watchdog Output protected against short circuit Wide temperature range: -40 C to 150 C Overtemperature protection Overload protection
P-DSO-12
Functional Description The TLE 4473 is a monolithic integrated voltage regulator with two very low drop outputs, a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum of 190 mA. The stand-by regulator transforms an input voltage VI in the range of 5.6 V VI 42 V to VQ2 = 5.0 V (2%) output voltage. The main output is tracked to the stand by output voltage and provides also 5 V. Versions of the device with 5 V/3.3 V and 5 V/2.6 V are available, please refer to the data sheet TLE 4473 G V53/TLE 4473 G V52. Two Inhibit Pins allow to use either both output voltages or to disable only Q1 or to switch off both outputs, the latter causing the current consumption to drop below 1 A. The TLE 4473 is designed to supply microprocessor systems and sensors under the severe conditions of automotive applications and is therefore equipped with additional protection functions against overload, short circuit and overtemperature. The device operates in the wide junction temperature range of -40 C to 150 C.
Type TLE 4473 GV55-2
Target Data Sheet
Ordering Code on request
1
Package P-DSO-12-4
Marking TLE4473GV55-2
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller Reset and Watchdog Behavior The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2 (`reset condition') a fast discharge of the delay capacitor CD2 sets in and as soon as VD2 gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay capacitor charge is the reset delay time. For the power-on case the charging process of CD2 starts from 0 V, which leads to the equation:
C D2 x V DU2 t D, on = ---------------------------I DC2
for the power-on reset delay time.
(1)
When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the watchdog circuit is enabled and discharges CD2 with the constant current IDD2. If there is no rising edge observed at the watchdog input, CD2 will be discharge down to VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the current IDC2 until VD2 reaches VDU2 and reset will be set high again. If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2, the periodical cycle starts again. The watchdog timing is shown in Figure 1. The maximum duration between two watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher capacitances on pin D2 result in longer watchdog trigger times:
T WI,tr
max
= 0.34 ms/nF x C D2
(2)
If the output voltage Q1 decreases below VRT1 (typ. 4.65 V), the external capacitor CD1 is discharged by the reset generator of the main output. If the voltage on this capacitor drops below VDL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises above the reset threshold, CD1 will be charged with the constant current IDC1. After the power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of CD1 using the above given equation (1) analogous for Q1.
Target Data Sheet
2
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
VW
V
t
VQ
T WD, p
t
VD2 VDU2 VDL2 VRO2
T WI, tr
t
t WD, L
t
T WI, tr =
(VDU2 -VDL2 )
DD2
C D2 ; T WD, p =
(VDU2 -VDL2 ) ( DC2 + DD2 )
DC2 x DD2
C D2 ; t WD, L =
(VDU2 -VDL2 )
t
DC2
C D2
AED03099_4473
Figure 1
Watchdog Timing Schedule
Target Data Sheet
3
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
TLE 4 4 7 3 GV5 5 -2
V Bat
7I
Q2 4 10 F Ove rte mp e ra tu re Sh u td o w n Ba n d g a p R e fe re n ce C u rre n t a n d Sa tu ra tio n C o n tro l, Ove rcu rre n t Pro te ctio n 4 .7 k R e se t Ge n e ra to r R O2 3
100 nF
CI
C Su p p ly
C R e se t
Ig n itio n
9 IN H 2
In h ib it
Wa tch d o g
WI 1 D2 11 100 nF
Wa tch d o g (fro m C )
Q1 6 10 F C u rre n t a n d Sa tu ra tio n C o n tro l, Ove rcu rre n t Pro te ctio n 8 IN H 1 4 .7 k R e se t Ge n e ra to r R O1 2
e .g . Se n so r Su p p ly
e .g . Se n so r R e se t (to C )
C
In h ib it D1 10 100 nF 12
TL E44 7 3G V5 5-2_ BLO CKDIAG RAM .VSD
GN D
Figure 2
Block Diagram with Typical External Components
Target Data Sheet
4
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Application Information The output voltage is divided by a voltage divider and compared to an internal reference voltage. A regulation loop controls the Q2 output in order to achieve a stable output voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference voltage for the Q1 is the regulated Q2 potential (tracking regulator). Figure 2 includes the components needed for a typical application. Maintaining the stability of the regulation loops requires a capacitor of 10 F both outputs. A maximum ESR of 5 is permissible for the Q2 output, while the Q1 output requires a capacitor with a maximum ESR of 3 . For both output blocking capacitors it is recommended to use tantalum types in order to stay in the permissible ESR range over the full operating temperature range. At the input of the regulator a capacitor is necessary for compensating line influences. A minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation of long input lines of several meters an electrolytic input capacitor of 47 F ... 220 F should be placed at the input.
TLE 4473 GV55-2 (P-DSO-12)
WI RO1 RO2 Q2 N.C. Q1
1 2 3
TL E4 4 73 GV5 5 -2 _PIN OU T.VSD
12 11 10 9 8 7
GND D2 D1 INH2 INH1 I
4 5 6
Figure 3
Pin Configuration (top view)
Target Data Sheet
5
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 1 1 2 3 4 5 6 WI RO1 RO2 Q2 N.C. Q1
Pin Definitions and Functions Watchdog input; input for watchdog pulses, positive edge triggered. Reset and watchdog output for Q1; open collector output. Connect to pull-up resistor. Reset output 2; open collector output. Connect to pull-up resistor. Stand-by regulator output voltage; block to GND with a capacitor CQ2 10 F, ESR < 5 at 10 kHz. Internally not connected; connect to GND. Main regulator output voltage; output voltage tracked to Q2 voltage; block to GND with a capacitor CQ1 10 F, ESR < 3 at 10 kHz Input voltage; block to ground directly at the IC with a ceramic capacitor. Inhibit input 1; low level disables Q1, integrated pull-down resistor. Inhibit input 2; low level at INH2 and INH1 disables Q2 and Q1, integrated pull-down resistor. Reset Delay 1; connect to ground via a capacitor to set reset delay for Q1. Reset Delay 2; connect to ground via a capacitor to set reset delay and watchdog timing for Q2. Ground; connect to heatslug. Interconnect heatsink area and GND.
Pin No. Symbol Function
7 8 9 10 11 12 Heatslug
I INH1 INH2 D1 D2 GND
Target Data Sheet
6
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 2
Absolute Maximum Ratings
-40 C < Tj < 150 C Parameter Input I Voltage Current Stand-by Output Q2 Voltage Current Main Output Q1 Voltage Current Inhibit Input INH1 Voltage Current Inhibit Input INH2 Voltage Current Reset Output RO1 Voltage Current Reset Output RO2 Voltage Current Reset Delay D1 Voltage Current Reset Delay D2 Voltage Current Symbol Limit Values Min. Max. 45 - 18 - 18 - 45 2 45 2 18 - 18 - 7 5 7 5 V mA V mA V mA V mA V mA V mA V mA V mA V mA - Internally limited - Internally limited - Internally limited - - - - - Internally limited - Internally limited - - - - Unit Remarks
VI II VQ2 IQ2 VQ1 IQ1 VINH1 IINH1 VINH2 IINH2 VRO1 IRO1 VRO2 IRO2 VD1 ID1 VD ID
-42 - -0.3 - -0.3 - -42 -2 -42 -2 -0.3 - -0.3 - -0.3 -5 -0.3 -5
Target Data Sheet
7
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 2
Absolute Maximum Ratings (cont'd)
-40 C < Tj < 150 C Parameter Watchdog Input WI Voltage Current Temperatures Junction temperature Storage temperature Table 3 Parameter Input voltage Junction temperature Junction pin Junction ambient Junction ambient Junction ambient Junction ambient Symbol Limit Values Min. Max. 7 5 150 150 V mA C C - - - - Unit Remarks
VRADJ IRADJ Tj Tstg
-0.3 -5 -50 -50
Operating Range Symbol Limit Values Min. Max. 42 150 4 115 100 60 48 V C K/W K/W K/W K/W K/W - - - PCB Heat Sink Area 0 mm2 1) PCB Heat Sink Area 100 mm2 1) PCB Heat Sink Area 300 mm2 1) PCB Heat Sink Area 600 mm2 1) 5.6 -40 - - - - - Unit Remarks
VI Tj Rthj-pin Rthj-a Rthj-a Rthj-a Rthj-a
Thermal Resistances P-DSO-12-4
1) Package mounted on PCB 80 x 80 x 1.5 mm3; 35 Cu; 5 Sn; zero airflow.
Note: In the operating range the functions given in the circuit description are fulfilled. Integrated protection functions are designed to prevent IC destruction under fault conditions. Protection functions are not designed for continuous repetitive operation.
Target Data Sheet
8
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 C < Tj < 150 C; unless otherwise specified
Parameter Stand-by Regulator Output Q2 Output voltage Output current limitation Symbol Limit Values Min. Typ. Max. Unit Test Condition
VQ2 IQ2
4.90 200 - - - -
5.0 300 200 15 5 65
5.10 550 600 50 20 -
V mA mV mV mV dB
1 mA < IQ2 < 190 mA; 6 V < VI < 28 V
VQ2 = 4.5 V IQ2 = 100 mA1)
1 mA < IQ2 < 190 mA
Output drop voltage; VDRQ2 VDRQ1 = VI1 - VQ1 Load regulation Line regulation VQ2,Lo VQ2,Li
Power Supply Ripple PSRR Rejection Current Consumption Quiescent current; stand-by Iq = II - IQ2
IQ2 = 1 mA; 6 V < VI < 28 V fr = 100 Hz; Vr = 1 Vpp IQ2 = 500 A; Tj = 25 C; VINH1 < VINH1 OFF (Q1 off) IQ2 = 500 A; Tj = 85 C; VINH1 < VINH1 OFF (Q1 off) IQ2 = 500 A; VINH1 < VINH1 OFF (Q1 off) IQ2 = 100 mA; VINH1 < VINH1 OFF (Q1 off) VINH1 = VINH2 = 0 V; Tj < 85 C VINH1 = VINH2 = 0 V
Iq
- - - -
170 - - 4.5 0.1 0.1
220 245 280 5 1 15
A A A mA A A
Quiescent current; inhibited
Iq
- -
Target Data Sheet
9
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont'd)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 C < Tj < 150 C; unless otherwise specified
Parameter Inhibit Input INH2 Turn-on Voltage Turn-off Voltage H-input current L-input current Charge current Discharge current Upper timing threshold Lower timing threshold Saturation Voltage Watchdog trigger time Reset delay time Reset reaction time Reset Output RO2 Reset switching threshold Reset threshold headroom Reset output sink current Reset output low voltage Reset high voltage Symbol Limit Values Min. Typ. - - 3.2 0.1 9.0 3.5 1.85 0.4 - 42 20 - 4.65 93 350 - 0.15 - Max. 2.3 - 6 1 12.5 5.0 2.4 0.5 100 51 25 5.0 4.8 96 500 - 0.3 - V V A A A A V V mV ms ms s V % mV mA V V Unit Test Condition
VINH2 ON VINH2 OFF IINH2 ON IINH2 OFF IDC2 IDD2 VDU2 VDL2 VD2,SAT TWI,tr TRD2 Trr VRT2 VRT2/VQ2 VR2HEAD IRO2 VRO2L VRO2H
- 0.65 -1 -1 6.5 2.0 1.5 0.3 - 34 15 - 4.5 90 200 1.6 - 4.5
VQ2 on VQ2 off VINH2 = 5.0 V (see
Page 13) 0 V < VINH2 < 0.8 V
Watchdog and Reset Timing D2
VD2 = 1 V VD2 = 1 V
- -
VQ2 < VRT2 CD2 = 100 nF CD2 = 100 nF CD2 = 100 nF
- -
VQ2 - VRT2 VQ2 = 5 V, VD2 = 0 V; VRO2 = 0.3 V VQ2 1 V; IRO2 = 1 mA RRO2,ext = 4.7 k
Target Data Sheet
10
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont'd)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 C < Tj < 150 C; unless otherwise specified
Parameter Symbol Limit Values Min. Main (Tracked) Regulator Output Q1 Output voltage Output voltage tracking accuracy Output voltage tracking accuracy Output current limitation Output drop voltage VDRQ1 = VI - VQ1 Load regulation Line regulation Typ. Max. Unit Test Condition
VQ1
4.875 5.0 5 5 500 300 5 5 65
5.125 V 25 25 - 600 50 25 - mV mV mA mV mV mV dB
1 mA < IQ1 < 200 mA; 6 V < VI < 28 V 1 mA < IQ1 < 200 mA; 6 V < VI < 28 V 1 mA < IQ1 < 300 mA; 8 V < VI < 28 V
VQ = -25 VQ2 - VQ1 VQ = -25 VQ2 - VQ1
IQ1 VDRQ1
VQ1,Lo VQ1,Li
350 - - - -
VQ1 = 4.5 V IQ1 = 200 mA1)
5 mA < IQ1 < 300 mA
Power Supply Ripple PSRR Rejection Current Consumption Quiescent current; Iq = II - IQ1 - IQ2 Quiescent current; Iq = II - IQ1 - IQ2 Inhibit Input INH1 Turn-on Voltage Turn-off Voltage H-input current L-input current
IQ1 = 5 mA; 6 V < VI < 28 V fr = 100 Hz; Vr = 1 Vpp IQ1 = 300 mA; IQ2 = 500 A; VQ1 and VQ2 on IQ2 = IQ1 = 500 A; VQ1 and VQ2 on VQ1 on VQ1 off
3.0 V < VINH1 < 5 V; (see Page 14) 0 V < VINH1 < 0.8 V
Iq
-
10
20
mA
Iq
-
250
500
A
VINH1 ON VINH1 OFF IINH1 ON IINH1 OFF
- 0.7 -1 -1
- - 3.5 0.1
2.3 - 5 1
V V A A
Target Data Sheet
11
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Table 4
Electrical Characteristics (cont'd)
VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 C < Tj < 150 C; unless otherwise specified
Parameter Reset Timing D1 Charge current Upper timing threshold Lower timing threshold Saturation Voltage Reset delay time Reset reaction time Reset Output RO1 Reset switching threshold Reset threshold headroom Reset output sink current Reset output low voltage Reset output high voltage Symbol Limit Values Min. Typ. 8.0 1.8 0.4 - 20 - 4.65 93 350 - 0.15 - Max. 12.0 2.2 0.6 100 30 10 4.8 96 500 - 0.3 - A V V mV ms s V % mV mA V V Unit Test Condition
IDC1 VDU1 VDL2 VD1,SAT TRD1 Trr VRT1 VRT1/VQ1 VR1HEAD IRO1 VRO1L VRO1H
4.0 1.6 0.3 - 14 - 4.5 90 200 1.6 - 4.5
VD1 = 1 V
- -
VQ1 < VRT1 CD1 = 100 nF CD1 = 100 nF
- -
VQ1 - VRT1 VQ1 = 5.0 V; VQ2 = 5.0 V; VD1 = 0 V; VRO1 = 0.3 V VQ1 1 V IRO1 = 1 mA RRO1,ext = 4.7 k
1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input)
Target Data Sheet
12
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Typical Performance Characteristics Output Voltage VQ2 versus Input Voltage VI
VQ2
8 V 7 6 5 4 3 2 4 .9 5 1 0 4 .9 0 -4 0 5 .0 0 5 .0 5
A E D 0 3 3 5 3 .V S D
Output Voltage VQ2 versus Junction Temperature TJ
VQ2
5 .1 5 V 5 .1 0
A E D 0 3 3 5 2 .V S D
R V
Load IN H 2
= 50 =5V
0
1
2
3
4
5
6
V
8
0
40
80
C
160
VI
Tj
Reset Thresholds VRT1, VRT2 versus Junction Temperature TJ
4 .8 0 V 4 .7 5
A E D 0 3 3 5 4 .V S D
INH2 Input Current versus Inhibit Voltage
I IN H 2
8 A 7 6
A E D 0 3 3 5 1 .V S D
V RT1, V R T2
4 .7 0
5 4
4 .6 5
3 2
4 .6 0 1 4 .5 5 -4 0 0
0
40
80
C
160
0
1
2
3
4
5
6
V
8
Tj
V IN H 2
Target Data Sheet
13
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
INH1 Input Current versus Inhibit Voltage
I IN H 1
8 A 7 6 5 4 3 2 1 0
A E D 0 3 3 5 0 .V S D
0
1
2
3
4
5
6
V
8
V IN H 1
Target Data Sheet
14
Rev. 0.2, 2005-07-26
TLE 4473 GV55-2
Package Outline
0 +0.1 STANDOFF 2.35 0.1
A
(Mold)
B
0.25 +0.075
(Body)
(1.55)
-0.035
6.4 0.1 1)
2.6 MAX.
7.5 0.1 1)
1 5x 1 = 5 0.4 +0.13
0.8
0.1 12x 0.25
10.3 0.3
0.25 B
M
CAB
(4.4 Mold)
5.1 0.1 12
(1.8 Mold)
12 Index Marking
7
1 6 7.8 0.1 (Heatslug)
6
1 Heatslug
GPS09349
1) Does not include plastic or metal protrusion of 0.15 max. per side
8.1
4.5
1.67
0.65 MAX. 1
hlg09455
9.4
Footprint
Figure 4
P-DSO-12-4 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Target Data Sheet 15 Dimensions in mm Rev. 0.2, 2005-07-26
1.6 0.1 (Metal) 4.2 0.1 (Metal)
(Metal) 7
53
Edition 2005-07-26 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2005.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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